Conventionally, an integrated circuit with a Joint Test Action Group (JTAG) function (in other words, a substrate including a plurality of integrated circuits) is checked, for example, through a method as depicted in FIG. 6. FIG. 6 is a drawing for explaining a conventional integrated-circuit checking method. JTAG is standardized according to IEEE 1149.1-1990, for example.
As depicted in FIG. 6, a test-target device (board) 10 includes integrated circuits 11 to 15 to be checked, and the integrated circuits 11 to 15 are in a cascade connection. The integrated circuits 11 to 15 are varied in operation speed. The operation speed of the integrated circuit 11 is 1 megahertz, the operation speed of the integrated circuit 12 is 10 megahertz, the operation speed of the integrated circuit 13 is 5 megahertz, the operation speed of the integrated circuit 14 is 5 megahertz, and the operation speed of the integrated circuit 15 is 10 megahertz.
A Personal Computer (PC) 20 inputs check data to the test-target device 10 and obtains the output result from the test-target device 10, thereby checking the integrated circuits 11 to 15 mounted on the test-target device 10. FIGS. 7A and 7B are drawings of an example of the check data employed to check the integrated circuit. FIG. 7A is a drawing of an example of the check data when all of the integrated circuits 11 to 15 are checked. FIG. 7B is a drawing of an example of the check data when only the integrated circuit 13 is checked.
In FIGS. 7A and 7B, check data A to E are data for checking the integrated circuits 11 to 15, respectively. Headers A to E are control data corresponding to the check data A to E, respectively. When checking the integrated circuits 11 to 15, the PC 20 obtains the check result by letting the check data depicted in FIG. 7A pass through the integrated circuits 11 to 15.
Also, when checking any one of the integrated circuits 11 to 15 (for example, when checking the integrated circuit 13), the PC 20 obtains the check result by letting the check data depicted in FIG. 7B pass through the integrated circuits 11 to 15. Here, the operation speed when the PC 20 performs a check (in other words, data transfer rate of the check data) is equal to the slowest one of the operation speeds of the integrated circuits 11 to 15.
Another technology for an integrated-circuit check has been known in which a test signal is detected by a JTAG test node and a route for each integrated circuit is selectively controlled according to the detected test signal (for example, refer to Japanese Translation of PCT International Application (Kohyo) No. 2006-519388).
However, in the conventional technologies explained above, JTAG-function-provided integrated circuits cannot be efficiently checked, and disadvantageously requiring a long time for check.
For example, when a failure occurs in an integrated circuit after shipment of the product due to a temporary contact failure because of a soldering failure of a specific terminal of the integrated circuit, an attachment of dust, or others, there is no measure of on-site checking of normality of a connection state between specific terminals of each integrated circuit at the time of occurrence of a failure. When the product is returned to a factory, even if a failure check is performed, the temporary failure occurring on-site cannot be reproduced, taking time to specify a failure portion.
Moreover, in checking the device having a failure in an integrated circuit, not a general PC but a check-dedicated PC including an external tester function has to be connected to the test-target device for performing these checks, thereby taking time for checks.
Furthermore, when the integrated circuits to be checked or to be written with data are in a cascade connection (for example, refer to FIG. 6), a check or data writing is performed at the slowest one of the data transfer rates of the integrated circuits, thereby requiring a long time for the check and data writing. In particular, a large amount of time is required when a large amount of data is to be written in an integrated circuit.
Also, normally, JTAG interfaces are in a cascade connection with a PC as a starting point. When a malfunction (a connection miss, a device failure, etc.) occurs at any point connecting the integrated circuits, it is difficult to specify where the malfunction occurs. To specify a suspected failure point, a procedure of cutting off an arbitrary JTAG route among the integrated circuits and returning the route back to a PC side has to be repeated, taking a long time to specify the failure point.